Unsupervised Machine Learning

State Elimination Method

4x2 Encoder using VHDL

Supervised Machine Learning

Proof of Arden's Theorem

1x4 Demultiplexer using VHDL

Making Predictions using ML Model

Arden's Theorem (Solved Problems)

1x2 Demultiplexer using VHDL

Saving Machine Learning Pipeline

Arden's Theorem

4x1 Multiplexer using VHDL

Model Evaluation in Machine Learning

Identities of Regular Expressions

2x1 Multiplexer using VHDL

Training a Machine Learning Model

Regular Languages to Regular Expressions

Carry Look-Ahead Adder using VHDL (Part 2)

Selecting a Machine Learning Algorithm

Designing Regular Expressions

Carry Look-Ahead Adder using VHDL (Part 1)

Feature Engineering in ML

Construction Rules of Regular Expressions

Ripple Carry Adder using VHDL

Data Preprocessing in ML - Practical

Introduction to Regular Expressions

Full Subtractor using VHDL

Data Preprocessing in ML

Conversion of Mealy to Moore Machine

Half Subtractor using VHDL

Digital Design Flow #VHDL #VLSI #NesoAcademy #QuickConcepts

Train-Test Split in ML

Conversion of Moore to Mealy Machine

Full Adder using VHDL

Data Cleaning in ML

Construction of Moore Machines

Half Adder using Dataflow Modeling in VHDL

Problem Definition and Data Collection in ML

Construction of Mealy Machines

Half Adder using Structural Modeling in VHDL

Machine Learning Pipeline

Moore Machines

Half Adder using Behavioral Modeling in VHDL

Performance Concepts in Machine Learning

Mealy Machines

Logic Gates using VHDL

Data Splitting

Finite Automata with Output

First VHDL Code in Vivado

Dataset Fundamentals